1. Field of the Invention
This invention relates generally to memory modules such as SIMMs and DIMMs utilizing signal processing elements, and more particularly to a more efficient technique for using signal processing elements in conjunction with memory busses in addressing memory chips on memory cards.
2. Background Information
The use of signal processing elements, such as digital signal processors (DSPs) on memory cards such as SIMMs or DIMMs is being done in order to use a relatively inexpensive processor for certain tasks on the memory card as well as to process information from the DRAMs on the memory cards while the memory bus is performing other tasks. For example a DSP can be used to perform speech recognition tasks, or translation tasks, or modem functions, all of which take a significant amount of time, and can tie up the system CPU if it is used for performing such tasks. Thus, the use of DSP""s frees the system CPU to perform other tasks while the DSP on the memory card is performing its assigned tasks involving the memory chips.
According to prior art proposals for DSPs either the memory bus (tied to the memory controller) or the memory card data bus (tied to the DSP on the memory card) has access to the memory chips, but not both. Thus while the system bus is accessing the DRAMs the DSP cannot perform its tasks. It is thus desirable that a technique be provided that will increase the time that a signal processing element can access the memory chips without interfering with the access of the memory bus.
According to the present invention an improved memory card and its use in a computer system is provided. The computer system has a system bus which provides requests from a CPU to a memory controller, which then provides signals to the memory card or module on a memory bus. The memory card is provided with first and second banks of DRAMs or other memory chips, a memory card bus and a signal processing element. Logic circuitry including a memory card data bus controller provides communication of the signal processing element with the banks of DRAM chips. Logic circuitry is also provided which can selectively connect or disconnect the signal processing element to either the first or second bank of DRAMs and selectively connect the memory bus with the other bank or both banks of DRAMs. Hence when the CPU is accessing one bank of DRAMS the DSP can access the other bank of DRAMs thus allowing the signal processor to function utilizing the bank of DRAMs not being accessed by the memory bus as a result of the CPU or some I/O device.